Electrical circuits requiring high power handling capability while operating at high frequencies, such as radio frequencies (500 MHz), S-band (3 GHz) and X-band (10 GHz), have become more prevalent in recent years. Because of the increase in high power, high frequency circuits, there has been a corresponding increase in demand for transistor amplifiers which are capable of reliably operating at radio and microwave frequencies while still being capable of handling high power loads.
A field effect transistor is a well-known type of transistor that is formed in a semiconductor structure. A source region, a drain region and a channel region are provided in the semiconductor material, with the channel region being between the source and drain regions. A gate electrode, which is often referred to as a gate finger, is formed above the channel region. The gate finger may be formed of a conductive material such as, for example, a semiconductor material, a metal or a metal alloy. A source contact is electrically connected to the source region and a drain contact (often referred to as a “drain finger”) is electrically connected to the drain region.
The power handling capabilities of a transistor may be a function of the gate periphery of the transistor, with larger gate peripheries corresponding to increased power handling capabilities. The gate periphery of a transistor refers to the distance that the gate finger extends between the source and drain regions. This distance is also referred to as the “width” of the gate finger. Thus, increasing the width of a gate finger is one technique for increasing the gate periphery, and hence the power handling capabilities, of a transistor. Another technique for increasing the effective gate periphery of a transistor is to provide a plurality of transistor cells that are electrically connected in parallel in a unit cell configuration to form a multi-cell transistor. For example, a high power multi-cell transistor may include a plurality of gate fingers that extend in parallel to each other. Each gate finger may define a separate unit cell transistor.
FIG. 1 is a schematic plan view of a conventional multi-cell transistor 1. As shown in FIG. 1, the conventional transistor 1 includes a plurality of gate fingers 30, a plurality of source fingers 40, and a plurality of drain fingers 50 that are formed on a semiconductor structure 10. The gate fingers 30 are spaced apart from each other along a first direction (e.g., the y-direction in FIG. 1) and extend in a second direction (e.g., the x-direction in FIG. 1). The gate fingers 30 are electrically connected to each other through a gate mandrel 32. The source fingers 40 are spaced apart from each other along the first direction and extend in the second direction. The source fingers 40 may be electrically connected to each other through vias or other structures (not visible in FIG. 1) and may be electrically connected to a source contact on the bottom side of the transistor 1 (not visible in FIG. 1). The drain fingers 50 are likewise spaced apart from each other along the first direction and extend in the second direction, and are electrically connected to each other through a drain mandrel 52. Each gate finger 30 extends in the x-direction between a pair of adjacent source and drain fingers 40, 50. The gate, source and drain fingers 30, 40,50 may each comprise a conductive material, such as a metal or a metal alloy.
In FIG. 1, a representative unit cell transistor 1 is illustrated at box 60 and may include a gate finger 30, the source and drain fingers 40, 50 on opposed sides of the gate finger 30, and the portion of the semiconductor structure 10 that underlies the gate, source and drain fingers 30, 40, 50. In many cases, one or more of the source fingers 40 and/or the drain fingers 50 (as well as the source regions and/or drain regions in the semiconductor structure 10 underneath the source and drain fingers 40, 50) may be shared by two adjacent gate fingers 30. As shown in FIG. 1, in such cases, each unit cell transistor 60 may be considered to include half of the shared source finger 40 and half of the shared drain finger 50. The “gate length” refers to the distance of the gate finger 30 in the y-direction, while the “gate width” is the distance by which the gate finger 30 overlaps (in plan view) with its associated source and drain fingers 40, 50 in the x-direction. Note that in many applications the “gate width” is much larger than the “gate length.” The gate periphery of the multi-cell transistor 1 is the sum of the gate widths for each unit cell transistor 60 thereof.
Multi-cell transistors that include a plurality of unit cell transistors that are electrically connected in parallel may be used in a variety of different applications, such as for DC amplifiers, RF amplifiers, switches and the like. Multi-cell transistors are often used in applications requiring high power handling capabilities as the unit cell structure increases the power handling capabilities of the device.